The present invention relates in general to a microcontroller interface to peripherals and, more particularly, to a serial peripheral interface with an embedded addressing scheme.
Microcontrollers and other microprocessors are used in a myriad of applications to control external devices. For example, a microcontroller may control the various system functions of a vehicle. Alternatively, a microprocessor controls peripheral chips in a computer system. The microcontroller communicates with the external device through a serial peripheral interface (SPI). The microcontroller typically has an SPI and the external device has an SPI. The SPI is a standard that handles the communication protocol, signal level compatibility, data transfer, clocking, handshaking, and control and status interchange.
In one prior art application, the microcontroller has a serial output and chip select coupled to a peripheral device. The chip select enables the peripheral device to receive control data at its serial input from the serial output of the microcontroller. The control data configures or controls the peripheral device. When there are multiple peripheral devices, the chip select is routed to a multiplexer having one input and several selectable outputs, one for each peripheral device. An address signal from the microcontroller selects one of the multiplexer outputs to enable the desired peripheral device. The selectable chip select solution adds components and complexity, i.e. the multiplexer and addressing, to the overall design.
Alternatively, the peripheral devices are cascaded with the serial output of one device coupled to the serial input of the next device in the chain. The serial output from the microcontroller is coupled to the serial input of the first peripheral device in the chain. The chip select enables all peripheral devices. The peripheral devices are addressed by the control data bits. The control data from the microcontroller is serially clocked through each peripheral device in the chain so that the first control data output ends up in the last peripheral device and the last control data output ends up in the first peripheral device. If there are four cascaded peripheral devices and each device receives 8 bits of control data, then the microcontroller provides 32 bits of data over 32 clocks. The disadvantage of cascading the peripheral devices with a common chip select is the communication latency of writing long strings of control data bits to address and configure the peripheral devices.
Other prior art techniques of embedded addressing such as the controller area network (CAN) require permanent storage elements for the address programming to individualize multiple uses of the same peripheral device.
Thus, a need exists to simplify the control and reduce latency overhead in writing to peripheral devices through a serial peripheral interface.